The disclosed subject matter relates generally to integrated circuit device testing and, more particularly, to a method and apparatus for AC Scan (i.e., scan-based AC or high-speed testing) with distributed capture and shift logic.
One technique for characterizing integrated circuit devices is commonly referred to as scan testing. In a scan topology, the flip flops of a logic unit are placed into a serial chain using alternate test mode routing circuitry, resulting in a circuit resembling a serial shift register with as many stages as the number of flip flops. Test patterns are shifted into the flip flops to test the logic circuitry of the device. After a test pattern is loaded into the flip flops, the response of the logic circuitry is captured in one or more of the flip flops using one or more scan clock pulses. After the results are captured, a new test pattern may be loaded into the flip flops for another test iteration while shifting out responses for the previous test pattern.
Typical devices employing scan based testing use an external clock to load the data and capture the results. This approach reduces the realism of the characterization or testing. Interactions between modules are difficult to identify and the device is not tested at its rated speed.
Some approaches deliver test patterns using by a scan clock at low speeds and test the speed paths (i.e., AC scan) of the chip using two faster clocks. The amount of time between the last scan clock and the first of the two fast clocks is normally large compared to the period of the two fast clocks, thus impacting the electrical characteristics of the circuit during test as compared with those seen during normal operation.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.